RTL Design Engineer (Santa Clara)

We are looking for an experienced RTL Design Engineer with a strong background in high-speed digital design and SerDes development.

Hiring: RTL Design Engineer Santa Clara, CA Contract – 12+ Months

Required Qualifications: MS in Electrical Engineering 8+ years of experience in SerDes, Microcontroller, or High-Speed Digital development Hands-on experience designing digital top-level ICs including analog/digital hard IPs, digital soft IPs, and custom design blocks Strong experience with microcontrollers Experience designing SerDes blocks such as link training, adaptation, calibration, CDR, and DSP-based equalizers Solid understanding of digital communication protocols including I2C, I3C, SPI, MDIO, UART, JTAG, etc. Active involvement across ASIC/SoC design phases: Architecture, RTL design, Verification, Synthesis, P&R, and STA Experience with low power design techniques, multi power domain design, clock gating, multi-VT design, DFx, CPF, and CDC tools

If you are interested or know someone who fits this profile, feel free to reach out directly or share your updated resume.