Job Description
Job Description:
Role: Senior IP Design Engineer
Type: Contract
Location: Belfast, UK Hybrid
Job details:
Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.
Key Skills:
SystemVerilog RTL design
100Gb Ethernet, PCIe Gen5, AMBA/AXI
Deep understanding xbpsjku of FPGA/Adaptive SoC design flow including
Please make an application promptly if you are a good match for this role due to high levels of interest.
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Job Details
Posted Date:
March 4, 2026
Job Type:
Construction
Location:
gb
Company:
Infoplus Technologies UK Ltd
Ready to Apply?
Don't miss this opportunity! Apply now and join our team.