Senior Digital Front-End ASIC Designer (RTL-to-GDS)

A premier research center in nanotechnology is seeking a Senior Digital Front-End Design Engineer in Naples, Italy. This role is crucial for ensuring high-quality design and implementation of complex ASIC designs. Candidates should have over 5 years of experience in front-end methodology, specifically in the RTL-to-GDS flow, alongside hands-on expertise in industry-standard tools like Cadence and Synopsys. The position offers a collaborative environment and a competitive salary with fringe benefits. #J-18808-Ljbffr