DFT Engineer

Job Title:

DFT Engineer Location:

Delhi NCR / Bangalore Experience:

8+ Years Notice Period:

Immediate to 15 Days

About the Role We are hiring an experienced

DFT Engineer

responsible for the complete design-for-test implementation and verification cycle for complex SoCs. The ideal candidate should have full-cycle experience across scan insertion, ATPG, LBIST, JTAG, and post-silicon debug, with strong exposure to industry-standard DFT tools and methodologies. Key Responsibilities End-to-end

DFT implementation and verification

for SoCs. Development and integration of

scan architecture, boundary scan, JTAG, MBIST, ATPG and LBIST . Hands-on execution of

scan insertion, ATPG DRC and coverage analysis . Run and debug simulation failures including

timing/SDF-based validation . Support

post-silicon debug, bring-up, and issue root-cause analysis . Collaborate with RTL, Physical Design, and Validation teams to ensure high-quality DFT closure. Required Skills & Expertise ✔ 10 years of experience in DFT engineering ✔ Proven experience working on

multiple SoCs end-to-end ✔ Strong hands-on experience in: Scan insertion JTAG, LBIST, MBIST ATPG pattern generation & validation ✔ Expertise in

Mentor Graphics DFT toolchain

and familiarity with

Synopsys scan insertion and timing analysis tools ✔ Strong understanding of

Verilog/VHDL RTL coding , automation, and linting flows ✔ Ability to debug simulation and silicon issues efficiently Preferred Attributes Strong attention to detail, proactive mindset, and ownership-driven work ethic Excellent verbal and written communication skills Passion for continuous learning, problem-solving, and cross-team collaboration Education BE / B.Tech / ME / M.Tech

in Electronics, Electrical, VLSI, or related engineering discipline from a reputed institution.

Regards Anil Sheoran anil@bestnanotech.in 9813621334