FPGA Design Engineer

Job Title: FPGA Design Engineer

Location: Bangalore / Hyderabad

Experience: 5 – 15 Years

Employment Type: Permanent / Contract (as applicable)

Notice Period: Immediate – 20 Days Only

Band: B2 / B3 / C1

About the Role

We are looking for a highly skilled FPGA Design Engineer with strong hands-on experience across the FPGA design flow, RTL design, timing, debugging, and high-speed interfaces. The ideal candidate should have deep expertise in Verilog/SystemVerilog, constraints, STA, CDC, and FPGA tools, with added advantage in telecom/5G domains.

Job Description

- Design, develop, and validate FPGA-based solutions - Perform RTL coding using Verilog/SystemVerilog - Work across the complete FPGA design flow: - RTL → Synthesis → Place & Route → STA - Handle CDC, RDC, lint, and RTL quality checks - Develop and apply timing and physical constraints - Debug FPGA designs using inbuilt logic analyzers (ILA, SignalTap, etc.) - Work with high-speed designs and standard bus protocols - Collaborate with validation, architecture, and system teams - Review FPGA design documents and support validation activities - Follow Agile development practices and version control (GIT)

Mandatory Skills

✔ Strong experience in FPGA Design & Architecture

✔ Solid understanding of FPGA design flow

✔ Expertise in Verilog / SystemVerilog RTL coding

✔ Hands-on experience with:

- CDC, RDC, Lint (Spyglass or equivalent) - STA & timing closure - Constraints development - ✔ FPGA debug using logic analyzers - ✔ Knowledge of high-speed FPGA design - ✔ Basic awareness of Zynq design flow - ✔ Strong logic design fundamentals - ✔ Experience with FPGA tools: - Lattice Radiant (Mandatory) - Intel (Quartus) - Xilinx / AMD (Vivado)

Good-to-Have / Added Advantages

➕ Experience in Telecommunication domain (5G, Radio Subsystems, AMS)

➕ Knowledge of bus protocols:

- AXI, AHB, APB, Avalon (AvMM) - ➕ Knowledge of PCIe IP integration - ➕ Experience with Ethernet - ➕ Knowledge of slow-speed protocols: - I2C, SPI, UART, MDIO - ➕ Understanding of error detection & correction - ➕ Scripting knowledge: - Make, Perl, Shell, Python - ➕ Experience working in Agile methodology

Tools & Technologies

- FPGA Tools: Lattice Radiant (Must), Intel Quartus, Xilinx/AMD Vivado - RTL Quality: Spyglass, CDC/RDC tools - Debug: ILA, SignalTap - Version Control: GIT - Scripting: Perl / Python / Shell

Important Note (Please Read Before Applying)

Do NOT apply if:

- You have less than 5 years or more than 15 years of FPGA experience - You do not have hands-on RTL FPGA design experience - You have a notice period longer than 20 days - You lack experience in FPGA tools and timing/constraints - You are from a non-FPGA background (verification-only, software-only, etc.)

✅ Apply ONLY if you meet ALL mandatory criteria.

Irrelevant profiles will not be process