R&D Integration Engineering - Sr. Director

ABOUT THE COMPANY:

Tata Semiconductor Manufacturing Private Limited (TSMPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

TSMPL (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

TSMPL is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’

RESPONSIBILITIES:

=>Technology Transfer & Readiness

- Lead the end-to-end technology transfer of 22nm and 28nm CMOS platforms from global partner foundries into TSMPL, ensuring full readiness for manufacturing, yield learning, and customer enablement. - Own transfer completeness, including process flows, integration assumptions, window margins, control plans, and manufacturability alignment. - Establish technology parity and gap-closure plans versus Tier-1 foundry benchmarks

=>New Technology R&D

- Technology/Business assessment of new platforms and features development at the 2X node. - This includes shrink of 28nm technology, enablement of RF and ULP/ULL features, new BEOL schemes, etc - Start to end ownership of the CMOS/RF projects at 2X node - Eventual transfer into Finfet R&D/transfer activities

=>Post-Transfer Yield Ramp & HVM Enablement

- Drive post-transfer R&D ownership to accelerate yield ramp, defect - density reduction, and variability control toward Tier-1 HVM standards. - Lead systematic yield-learning loops using inline, E-test, PCM/WAT, and failure analysis data. - Ensure technology robustness across process corners, layout sensitivities, and product use cases

=>Device Performance & PPA Enhancement

- Spearhead performance-boosting R&D initiatives beyond baseline transfer targets, including leakage reduction, drive current enhancement, variability control, and RF and power device Figures of Merit (FOMs) - Align integration decisions with PPAC (Power, Performance, Area, Cost) optimization targets.

=>Integration Architecture Ownership

- Define and own holistic FEOL–MOL–BEOL integration architecture, ensuring module compatibility, robust process windows, and scalable manufacturability - Optimize process integration for automotive-grade, HPC, RF, and mixed-signal applications.

=>Cross-Functional Technical Leadership

- Orchestrate cross-functional execution across Lithography, Etch, CMP, Implant, Deposition, Metrology, Reliability, and Yield teams. - Serve as the integration authority to resolve trade-offs between device design, process capability, yield, and reliability.

=>Reliability & Qualification

- Accountable for technology qualification, including automotive-grade reliability and long-term robustness for storage and wireless applications. - Ensure compliance with industry qualification standards and customer expectations

=>Benchmarking, Roadmap & Stakeholder Interface

- Drive continuous competitor benchmarking against Tier-1 foundries to define improvement targets and roadmap priorities. - Act as the primary technical interface to executive leadership, customers, and strategic partners. - Own technology readiness milestones, risk mitigation strategies, and executive reporting.

=>Advanced Node & FinFET Readiness

- Oversee test structure, E-test vehicle, and test-chip design to validate new integration schemes. - Lead early FinFET prototyping readiness, ensuring smooth architectural migration from planar to advanced transistor structures. - Build strong customer relationships based on confidence in TSMPL technical capabilities.

=>Presentation to internal and customer senior executives

=>Travel – as necessary

ESSENTIAL ATTRIBUTES:

1. Ability to manage, mentor, and lead a team of highly motivated professionals. 2. Able to work independently, self-motivated with a strong drive to win. 3. Team player with the ability to work across diverse cross-functional teams spread across the world. 4. Leadership skills to influence all levels of the organization. 5. You’re inclusive, adapting your style to the situation and diverse global norms of our people. 6. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 7. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 8. Innovative and creative, you proactively explore new ideas and adapt quickly to change. 9. Tier-1 Execution Mindset: Deep understanding of what constitutes production-worthy technology at leading foundries.

Integrity & Trust: Demonstrates mission-driven leadership with strong ownership and accountability.

QUALIFICATIONS:

1. M.S. or Ph.D. in Electrical Engineering, Materials Science, Engineering Physics, Chemical Engineering, or a related field. 2. Deep expertise in CMOS technology integration, including device physics and process interactions. Has directly worked on planar HKMG structures, SiGe stressors, BEOL integration schemes, etc at 2X nodes 3. Strong working knowledge of SRAM, logic, RF, power devices, and eNVM integration considerations; experience in achieving competitive performance 4. Proven capability to guide TCAD, compact modeling, and variability modeling teams to align prediction with silicon. 5. Advanced understanding of failure mechanisms, reliability physics, and analytical techniques. 6. Demonstrated success managing large, complex R&D programs with tight timelines and business impact. 7. Strong understanding of device physics, process modules, yield improvement, failure mechanisms, analytical techniques (physical and electrical) 8. Proven track record in developing and transferring technologies into high volume manufacturing 9. Can guide team to design and layout E-test structures and analyze/interpret data from these structures 10. Familiarity with Finfet structures 11. Ability to lead cross-functional teams and achieve project completion within timeline and cost targets 12. Ability to work across different cultures and geographies 13. Innovation mindset

DESIRED EXPERIENCE:

1. 15+ years of semiconductor industry experience. 2. Significant tenure in a Tier-1 foundry or leading IDM environment. 3. Proven track record of: Technology transfer, Yield ramp to HVM, Post-transfer performance enhancement, and developing new technologies into high volume production 4. Experience with 22nm / 28nm nodes is required; FinFET experience is strongly preferred.

Prior leadership at Director / Sr. Director / AVP level with responsibility for large technical organizations.