Design Verification Engineer

Job Title:

Low-Power SoC DV Engineer

Experience:

5+ Years Location:

Bangalore

Job Overview: We are looking for an experienced

Low-Power SoC Design Verification (DV) Engineer

with strong expertise in full-chip and sub-system level verification, particularly in low-power methodologies using UPF.

Mandatory Skills & Experience: Strong experience in

full-chip SoC and/or sub-system level verification with UPF Experience in VIP development or only IP-level verification

will not be considered

. If experience includes both IP and SoC/sub-system verification, at least

70–80% of the work must be SoC/sub-system + UPF verification

. Hands-on experience in

testbench (TB) development from scratch

or development of major TB components such as: Scoreboard Drivers Sequencers Checkers Agents Ability to: Understand design specifications Develop detailed

test plans

covering features and verification scenarios Implement verification strategies for SoC/sub-system level designs Strong experience with: SpyGlass

for static UPF checks Developing functional tests for

dynamic power checks Excellent debugging skills using: Verdi / Verisium / SimVision

for waveform analysis and debugging

Preferred Skills: Strong analytical and problem-solving skills Experience in low-power architecture validation Good communication and documentation skills