FPGA Sr. Design Engineer

FPGA Sr. Design Engineer – 5G / ORAN/PCIE/high speed Experience Mandatory Location:

Chennai & Bangalore Experience:

6–10 years Qualification:

BE/B.Tech/M.E/M.Tech or equivalent About the Role We are looking for an experienced

FPGA Sr. Design Engineer

with strong expertise in

5G or ORAN

technologies. The role involves designing, implementing, and testing FPGA-based hardware systems f along with R&D activities for proof-of-concept demonstrations. Key Responsibilities Implement FPGA code on target hardware and test with system components/software. RTL Design, Implementation, Testing, Integration, and delivery of FPGA-based systems. Participate in R&D for aerospace-related design techniques. FPGA RTL Design experience. - System Verilog, VHDL, UVM/OVM, Python/PERL/TCL - FPGA verification flow experience (Xilinx Vivado, Intel Quartus, Lattice, QuestaSim, ModelSim, etc,..) - LTE/4G/5G, ORAN, CPRI, FHGW, DO-254, etc,.. - Zynq UltraScale+ RFSoC, Virtex7, Aria10, MPSoC, Spartan etc,.. - IIC, ARINC, SPI, UART, MIL-1553, Ethernet, AHB, ABP, AXI, etc,.. Domain Expertise Proficient in FPGA design flows using

Xilinx tools

(compilation, simulation, synthesis, debugging, optimization). Strong knowledge of

Verilog, VHDL, SystemVerilog . Experience integrating

Soft IP/Hard IP

(GTX/GTH transceivers, MAC, DMA, PCIe Gen3, CPRI, JESD, FFT IP cores). Skilled in verification environments with

self-checking testbenches, BFMs, checkers, monitors, scoreboards . Familiar with control interfaces:

AMBA AXI, UART, SPI, I²C, DDR, Ethernet, USB . Hands-on with hardware debugging tools:

oscilloscopes, signal analyzers, JTAG emulators . Experience with

Vivado/Vitis

and evaluation kits. Good to Have Scripting skills:

Perl, TCL, Python

for automation. Exposure to FPGA bring-up procedures and testing methodologies. Knowledge of

linting, STA, equivalence checking, CDC verification .