Design Verification Engineer

#ACL Digital is hiring: IP Verification Engineer – UVM Verification We are looking for engineers with strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience. Hands-on expertise in AXI4, NoC protocols, and multi-master/multi-slave configurations is required. Experience with DRAM memory controllers, traffic patterns, bandwidth & latency analysis is a plus. Proficiency with VCS/Questa/Xcelium/Riviera and Vivado debug is essential.

Experience: 5–7 years Notice Period: Immediate / 30 days