RTL Design Engineer – ASIC / SoC

Hi We are hiring a hands-on ASIC RTL engineer with strong RTL coding skills who owns micro-architecture and RTL development from spec to silicon. This role is about writing real RTL that goes into production chips.

Mandate

Define and own micro-architecture Write, review, and own high-quality synthesizable RTL code in SystemVerilog / Verilog Build and integrate SoC or large subsystem blocks Drive timing, power, and area closure with physical design teams Lead design reviews, debug issues, and support silicon bring-up and post-silicon validation Work closely with DV on test plans, assertions, and coverage FPGA/emulation may be used only as a secondary validation aid

What we’re looking for

8+ years of hands-on ASIC RTL coding experience (FPGA experience does not count toward this requirement) Multiple production ASIC tapeouts with clear ownership Strong RTL coding and micro-architecture ownership (non-negotiable) Solid understanding of clock/reset design and low-power techniques (UPF, retention, isolation) Experience with AMBA protocols: AXI, ACE, AHB, APB Proven collaboration with synthesis, PnR, DFT, ECO, and timing-closure teams Direct silicon bring-up experience for owned blocks

Good to have Exposure to coherency, cache/memory subsystems, DDR, PCIe, security or crypto blocks SVA for design-level assertions Tcl/Python scripting to improve RTL productivity

Cheers, Shahid