Design Engineer

RTL Lead Engineers Experience : 8 years Location : Bangalore

8+ years of solid RTL design experience. - RISC-V CPU core design involving CSRs, Load Store, MMU, IO-MMU, Fetch, and Debug. - ACE/CHI/AXI protocol and NOC Architecture. - RISC-V Coherency manager block RTL modification and performance-related features. - Designing TRU blocks for debug tracing based on the RISC-V NEXUS trace spec. - AIA block RTL development, debug, and trace RTL. - RISC-V CPU core design involving FPU (IEEE 754) IP. - Non-standard extension for single precision float (“F”) implementation.

Interested,please share your updated resume to janagaradha.n@acldigital.com