Principal STA /Synthesis Engineer

About the Company

Cadence HYD is Hiring STA/Synthesis Lead principal Engineer

About the Role

Cadence is in search of an STA Engineer proficient in SDC checks and timing closure for intricate semiconductor designs. The ideal candidate will:

Responsibilities

Develop and validate SDC files for clocks and exceptions Address timing issues by analyzing STA reports and PPA Collaborate with RTL, synthesis, and physical design teams and Low power Possess strong scripting abilities in TCL/Python

Qualifications

Experience: 8-15 years Location: Hyderabad

Required Skills

Proficient in SDC checks and timing closure Strong scripting abilities in TCL/Python

Preferred Skills

Experience in collaborating with RTL, synthesis, and physical design teams

Apply: Send your updated profile to

Equal Opportunity Statement

If you are enthusiastic about timing analysis and eager to contribute to cutting-edge semiconductor designs, we invite you to explore this opportunity with us. Let your expertise shine at Cadence!