Physical Design Engineer

Location: Hyderabad Notice Period: 0 to 45 Days 6+ years

of hands-on experience in

ASIC/SOC physical design . Strong expertise in

AMD physical design flow

and signoff tool chain. Proficiency in: Floorplanning, placement, CTS, routing Multi-mode multi-corner (MMMC) timing closure IR/EM analysis CLP/VCLP/FEV analysis Power/Clock/domain partitioning Experience with signoff tools like

Fusion compiler, PrimeTime, RedHawk, Calibre . Expertise in scripting languages:

Tcl, Perl, Python . Deep understanding of sub‑7nm design challenges (congestion, variability, advanced timing methodologies).