Design Verification Architect

Design Verification Architect Location:

Bengaluru, India Experience:

10–16 Years

About the Role: We are looking for a

Design Verification Architect

to lead the architecture and execution of verification strategies for next-generation high-performance silicon platforms. In this role, you will define scalable verification methodologies and drive end-to-end verification for complex

SoC/IP designs

involving high-speed interfaces such as

PCIe, DDR, and Ethernet . You will collaborate with architecture, design, and system teams to build robust verification infrastructures using

SystemVerilog and UVM , enabling first-pass silicon success for cutting-edge semiconductor products. What You’ll Do Architect and drive end-to-end verification strategy

for complex SoC and IP designs. Define

scalable SystemVerilog/UVM based verification environments

and reusable frameworks. Lead verification of high-speed protocols such as

PCIe, DDR, and Ethernet

across subsystem and SoC levels. Develop advanced

testbench architectures, scoreboards, checkers, coverage models, and protocol monitors . Define

functional coverage, assertion-based verification, and debug methodologies

to ensure comprehensive verification closure. Work closely with design, architecture, and firmware teams to review specifications and improve design quality early in the lifecycle. Drive

verification planning, regression strategies, and performance verification

across large multi-IP SoCs. Mentor verification engineers and promote

best practices in UVM architecture and verification methodologies . Lead

silicon bring-up support and root-cause analysis

when needed. Basic Qualifications BS/MS/MTech in Electrical Engineering, Computer Engineering, or related field. 10–16 years of experience

in ASIC/SoC Design Verification. Expert-level proficiency in

SystemVerilog and UVM methodology . Strong experience verifying

high-speed protocols such as PCIe, DDR, and Ethernet . Deep understanding of

verification architecture, constrained random verification, coverage-driven verification, and assertions (SVA) . Experience building

scalable reusable UVM testbenches

for complex SoC environments. Strong debugging skills across

RTL, protocol, and system-level interactions . Preferred Qualifications Experience with

PCIe Gen4/5/6, DDR4/DDR5/LPDDR, and high-speed Ethernet (10G/25G/100G+) . Experience with

SoC-level verification, subsystem integration, and multi-IP environments . Familiarity with

formal verification, emulation, or FPGA prototyping . Strong scripting skills in

Python, Perl, or Tcl

for verification automation. Experience mentoring engineers and driving

architecture-level verification decisions .

About Us: Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people. Website https://