RTL Design Lead - SOC/Test chip

About Tata Electronics Private Limited

Tata Electronics Pvt. Ltd. is a prominent global player in the electronics manufacturing industry, with fast-emerging capabilities in Electronics Manufacturing Services, Semiconductor Assembly & Test, Semiconductor Foundry, and Design Services. Established in 2020 as a greenfield venture of the Tata Group, the company aims to serve global customers through integrated offerings across a trusted electronics and semiconductor value chain. With a rapidly growing workforce, the company currently employs over 65,000 people and has significant operations in Gujarat, Assam, Tamil Nadu, and Karnataka, India. Tata Electronics is committed to creating a socioeconomic footprint by employing many women in its workforce and actively supporting local communities through initiatives in environment, education, healthcare, sports and livelihood.

About the Job Description:

Job Overview:

Person will be responsible for developing multiple test chips for IP verification and drive optimized full-chip architecture for modular design. Will continue to push the boundaries of innovation by developing architectures that inherently support testability, with the objective of achieving zero-defect silicon. This will be driven by a "correct-by-construction" mindset throughout the design process. The role necessitates a comprehensive understanding and active involvement in all facets of VLSI development, including microarchitecture and platform architecture, front-end design, and design convergence. Additionally, the candidate will be responsible for overseeing the physical design and verification processes.

Job Description:

- Full chip design for multimillion gates SoC - Digital design and development (RTL) - Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification - Manage IP dependencies, planning and tracking of all front-end design related tasks - Driving the project milestones across the design, verification and physical implementations

Minimum Qualifications:

- Minimum 12 years of solid experience Test Chip / SoC design - Solid expertise and understanding of digital design concepts. - Developing architecture and micro-architecture from specs - Understanding of JTAG base test chip architecture for IP testability and enable programmable registers for IP testability - Ability to review full chip top level test plans - Hands-on working knowledge and expertise in FEV, Cadence LEC & Synopsys Design Compiler Synthesis. - Ability to make effective decisions, even with incomplete information when time is of essence. - Working knowledge of timing closure is a must. Work on key design collaterals such as SDC and UPF flows. - Work with key stakeholders like PD, DFT and Verification to discuss the right collateral quality and identify solutions/workarounds. - Demonstrated good post silicon bring up and debug experience - Demonstrated good SoC/ Test-Chip integration exposure and its challenges - Demonstrated good exposure to design verification aspects - Having SoC specification to GDS to commercialization experience is highly desired - Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas. - Provides direction, mentoring, and leadership to a small to medium sized groups. - Should possess strong communication and leadership skills to ensure effective communication with Program Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. - Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. - Conduct timely review of the RTL progress and work with program managers to provide weekly update on the progress towards RTL milestones completion. - Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design - Should possess expertise in front-end EDA tools sign-off and its flows. - Ability to program with scripting languages such as Python or Perl is a plus. - Highly motivated to seek out solutions and willing to learn new skills to fulfil job requirements. - Proven interpersonal skills, leadership and teamwork. - Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC - Understanding of Memory controller designs and Microprocessors is an added advantage - Understanding of Chip IO design and packaging is an added advantage