Principal RTL Design Engineer / Co-founder - AI/ML Accelerator

Job description Lead / Own a world class NPU for Edge AI Inference Develop ultra-low-power machine learning chips for intelligent sensing and autonomous navigation Architect / Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and micro architecture specifications. Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines. Work with Design Validation (DV) teams to create test plans for, verify, and debug design RTL. Work with physical design teams to ensure design meets physical requirements and timing closure. Key qualifications PhD or Master’s degree in electronics engineering or related technical field. Solid experience with machine learning algorithms and architectures i.e. LLM Transformer. You must have worked on in-memory computing. Experience in Emulation / Simulation, FPGA prototyping, digital IC design, RTL design, EDA design tools (Cadence or Synopsys) and methodologies. Experience in processor (ARM or RISC-V) design is a strong plus. Experience in machine learning FPGA implementation is a plus. 4 years of experience in digital/ASIC design using SystemVerilog or RTL. Experience in one or more successful ASIC products from concept to silicon. Experience interacting with software, system hardware, and other cross-functional teams. Experience defining SoC IP interfaces and methodologies. Understanding in computer architecture/memory subsystem (HBM) architecture. Someone who knows the complete market landscape of who's who of AI accelerators and performed gap analysis, market differentiation.

P.S. This is for someone who is mature enough with urge to do his/her startup and able to sustain with equity only (till we get external funding)