Lead Verification engineer

About the Company

Cadence is looking to hire Verification Engineers in Hyderabad with PCI protocol4-7 years of experience.

About the Role

The role involves the development of test plans, tests, and verification infrastructure for complex IP’s/sub-systems/SOC’s.

Responsibilities

Development of test plans, tests, and verification infrastructure for complex IP’s/sub-systems/SOC’s. Creation of verification environment using UVM methodology or equivalent. Construction of reusable bus functional models, monitors, checkers, and scoreboards. Leading functional coverage verification closure.

Qualifications

BTech/ MTech in Engineering.

Required Skills

4-7 years of VLSI industry experience in Verification. With experience in PCI protocol. Expertise in SoC level verification and IP/Subsystem validation. Proficiency in developing test bench/testbench components, test plans, test cases, functional coverage, assertions, and coverage analysis. Strong knowledge of UVM, SV. Familiarity with protocols like UCIe, PCIe, DDR, USB. Skilled individual contributor and mentor with exceptional debug and problem-solving abilities. Extensive experience in the verification cycle for complex SOCs.

Location: Hyderabad

To express interest, kindly share your updated profile at dsupriya@cadence.com