Verification Engineer

Project description

We are looking for a Verification Engineer to work on IP-level using a UVM-based environment. The role involves writing the test cases in UVM, performing functional Verification with RTL, and debugging issues to support timely delivery of IP

Responsibilities

# Build and maintain UVM-based IP-level verification environments using SystemVerilog.

# Verify RTL functionality, debug issues, and drive them to closure with design teams.

# Define and execute verification plans, tests, and coverage to ensure spec compliance.

# Collaborate with cross-functional teams to ensure timely and accurate verification sign-off.

# Own deliverables with a strong focus on quality, efficiency, and on-time completion.

Skills

Must have

7-8 years of experience in UVM-based IP-level verification.

Strong hands-on expertise in:

# System Verilog and UVM methodology

# RTL verification and debugging

Solid understanding of digital design concepts and verification methodologies.

Excellent communication and collaboration skills.

Ownership mindset with a focus on quality and timely delivery.

Nice to have

Good Knowledge Protocols ETHERNET, AXI,AHB

Experience with scripting languages (Python, Perl, Shell) for automation.