DFT Lead

Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC Design (Founding SoC Team) Role Overview As the DFT Lead , you will be the primary architect and owner of the testability strategy for our next-generation AI SOCs. This is a "zero-to-one" opportunity where you will bridge the gap between initial architectural concepts and final production silicon. You will ensure our high-performance AI/Networking chips meet the highest standards of test coverage, power efficiency, and manufacturing yield in a fast-paced startup environment. Key Responsibilities ● End-to-End Ownership: Define and drive the complete DFT strategy—from initial SoC specification through RTL, synthesis, and post-silicon validation. ● Architecture & Strategy: Architect comprehensive DFT solutions including Scan, MBIST (Memory Built-In Self-Test), JTAG, Boundary Scan, and high-speed IO testing tailored for AI workloads. ● Implementation Excellence: Lead the integration and verification of DFT structures (EDT, Compression, Hierarchical DFT) to optimize for both test time and silicon area. ● Cross-Functional Leadership: Partner closely with Physical Design teams to close timing on DFT paths and collaborate with Design/Verification teams to ensure test-friendly RTL. ● Pattern Generation & Simulation: Drive ATPG flows, including stuck-at, transition-delay, and cell-aware testing, ensuring ultra-high defect coverage. ● Execution & Tape-out: Manage the critical transition from pre-silicon simulations to post-silicon ATE (Automatic Test Equipment) bring-up and debug. ● Technical Mentorship: Build and mentor a lean, high-performing team of DFT engineers, establishing best-in-class tool flows and methodologies from scratch. Key Skills & Technical Requirements ● DFT Domain Expertise: Expert-level proficiency with Mentor Tessent (TK/IJTAG).

● Comprehensive Test Coverage: Deep experience in Scan Compression, MBIST, Hierarchical DFT, and IEEE 1687 (IJTAG) standards. ● Design & Timing: Solid understanding of RTL design (Verilog/SystemVerilog) and a sharp eye for the impact of DFT on Static Timing Analysis (STA). ● Scripting & Automation: Highly proficient in Tcl, Perl, or Python to automate complex DFT flows and pattern processing. ● Advanced Methodologies: Experience with BIST for High-Speed SerDes, HBM (High Bandwidth Memory), and thermal/power-aware testing for large-scale AI chips. ● Debug & Diagnosis: Strong hands-on experience in gate-level simulations (GLS) and silicon debug on the tester. Preferred Qualifications ● Academic Background: Master’s or PhD in Electrical/Electronics Engineering or a related field. ● Architectural Vision: Experience defining DFT architecture for multi-die or Chiplet-based designs. ● AI/High-Tech Exposure: Familiarity with high-power AI accelerators and their unique challenges (e.g., massive gate counts, power-hungry scan cycles). ● Startup Mindset: A proven ability to build flows from the ground up and thrive in a high-execution, high-growth environment.