Senior Engineer

Job Role : STA Engineer / Lead

Exp : 4 to 12 years

location : Bangalore

Preference : Immediate to 30days

Interested can share cvs to divya.lakshmi@acldigital.com

Requirements:

Deep understating and experience of STA tool #Tempus/ #PrimeTime / #Tweaker/ #DMSA(PTECO)

Knowledge of timing corners/modes, process variations and signal integrity related issues are required

Experience in timing closure of high frequency blocks & subsystems (Ghz range )

Experience in working full-chip STA closure, defining mode requirements and corners for timing closure.

Strong Understanding of DFT modes requirements for timing signoff

Good understanding of physical design flow and ECO implementation.

Strong understanding of SDC constraints, OCV,AOCV,POCV analysis.

Strong TCL/scripting knowledge is mandatory.