VLSI / RTL Design Engineer

We are global semiconductor company having world class team in Bangalore, India. And adding some of the best brains in R&D team in India.

Budget is around 80 to 95 L.p.a

As an RTL Design Engineer, you will be responsible for the micro-architecture and logic design of high-performance SoC modules. You will translate complex architectural specifications into efficient, synthesizable

Verilog/System Verilog

code. This role requires a deep understanding of the entire front-end flow, from initial RTL entry to hand-off for Physical Design, ensuring that designs meet stringent timing, area, and power targets.

Key Responsibilities Micro-Architecture Design:

Collaborate with architects to define module-level specifications and develop detailed micro-architecture documents. RTL Development:

Write high-quality, maintainable, and synthesizable code using

System Verilog

or

Verilog . Front-End Integration:

Perform Linting, Logic Equivalence Checking (LEC), and

Clock Domain Crossing (CDC)

analysis to ensure robust design quality. Collaboration:

Work closely with the Verification team to define test plans and debug RTL issues. Provide support to the Physical Design (PD) team to resolve synthesis and Static Timing Analysis (STA) bottlenecks. Post-Silicon Support:

Assist in silicon bring-up and work with Failure Analysis (EFA) teams to debug logic issues found in actual hardware.

Technical Qualifications Experience:

Minimum 7 years of proven experience in ASIC/VLSI design. Languages:

Expert-level proficiency in

SystemVerilog

and

Verilog . Tooling:

Hands-on experience with industry-standard tools Scripting:

Proficiency in

Python, Perl, or Tcl

to automate design tasks.

Preferred Skills Familiarity with Formal Verification techniques. Understanding of DFT (Design for Test) concepts and their impact on RTL

Education Bachelor’s or Master’s Degree in Electrical Engineering (EE), or Computer Engineering from a known university.