Lead Memory Design Engineer

Job Title:

Lead Memory Design Engineer Experience:

6+ Years Location:

Bangalore Employment Type:

Full-time Industry:

Semiconductors / VLSI / Memory IP / SoC Job Summary: We are looking for an experienced and highly motivated

Lead Memory Design Engineer

to drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and Register Files. The role involves leading a team of designers, interacting with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Key Responsibilities: Define architecture and design specifications for custom memory IPs or memory compilers. Design and optimize circuits such as: Memory cell arrays, sense amplifiers, precharge, write drivers, decoders, control logic Lead the schematic-level design and simulation (pre-layout and post-layout) for performance, power, and robustness. Collaborate with layout, verification, and technology teams to ensure full-cycle delivery. Guide post-layout activities including parasitic extraction, IR/EM analysis, and corner validation. Ensure designs meet requirements for DFM, yield, reliability, and aging. Contribute to methodology and flow development for memory design and characterization. Support silicon bring-up and correlation with pre-silicon simulation. Provide technical leadership and mentorship to junior engineers. Drive design reviews and coordinate with program managers for delivery timelines. Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering. 8+ years of experience in full-custom memory design (SRAM, ROM, CAM, Register Files). Solid understanding of CMOS analog/digital circuit design principles. Expertise in circuit simulation tools: Spectre, HSPICE, FastSPICE (XA, FineSim, etc.). Experience with advanced nodes (28nm, 16nm, 7nm, 5nm, FinFET). Hands-on experience with variation analysis (Monte Carlo, PVT), IR drop, and EM checks. Familiarity with memory characterization, yield analysis, and silicon debug. Strong analytical, communication, and leadership skills. Preferred Qualifications: Experience in memory compiler design and automation. Knowledge of low-power memory design techniques (multi-Vt, multi-Vdd, power gating). Experience with ECC, redundancy, and repair strategies. Familiarity with ISO 26262/Safety compliance (for automotive memory IPs). Scripting knowledge (Python, Perl, Tcl) for automation of design and simulation flows.

Interested can share Cv to Sharmila.b@acldigital.com