Pre-si performance / TLM modeling Senior Engineer

Job Description:

Work with Performance Models for the next generation System-on-chip (SoC) for smartphone, IoT, Auto and other product categories. Work with design team to develop IP Models for Peripherals like PCIe, Ethernet, USB, UFS. Develop the SoC platform and verify the IP/System Level use cases. Work with Hardware & Software teams to understand the design requirements, specification and interface details. You will have opportunity to suggest architecture and design changes which can optimize the overall power/performance/thermal for the chipset.

Some of the key skills which are required (1-2 key skills will be important): Experience in SystemC/TLM 2.0 modelling. Understanding of protocols in one of more IP’s like PCIe, CXL, Ethernet, USB and UFS will be desirable. Good understanding of C/C++ based model development and SoC integration. Good understanding of bus protocols like AXI, AHB, QSB Experience working in team where close collaboration is required between multiple stakeholders Understanding of DDR design and it’s performance aspects at SOC level Understanding of SOC DV/VI/RUMI/performance validation

Keywords : “TLM2.0 | Ethernet | PCIe | CXL”, “SystemVerilog & Ethernet & PCIe | CXL”.