Job Description
SoC DFT Engineer
Job Description:
Scan insertion.
SCAN DRC/Coverage debug.
ATPG Pattern generation.
Gate level simulations ( Zero delay/Timing Delay simulations).
Worked on JTAG/P1500 protocols.
Perl/Tcl scripting.
Timing/Formal verification/PD flow knowledge is plus.
Location: Bangalore
Notice Period: Immediate
Experience: 5+ Years
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Don't miss this opportunity! Apply now and join our team.
Job Details
Posted Date:
February 25, 2026
Job Type:
Construction
Location:
Bangalore, India
Company:
ACL Digital
Ready to Apply?
Don't miss this opportunity! Apply now and join our team.
