Semiconductor Testability Engineer

Company:Global Technology organization

Key Skills:

Scan Insertion, ATPG, DFT Design, MBIST, JTAG Roles and Responsibilities: Implement and verify DFT methodologies for HBM, DDR, and SerDes IP designs. Perform scan insertion, ATPG generation, and DFT architecture validation to achieve high test coverage. Collaborate with design and architecture teams to define and optimize testability requirements. Work closely with STA and design implementation teams to ensure design closure for test. Generate, verify, and debug test vectors prior to tape-out. Validate and debug test vectors on ATE during silicon bring-up. Support silicon failure analysis, diagnostics, and yield improvement initiatives. Interface with customers, physical design, and manufacturing/test engineering teams globally. Debug customer-returned parts using ATE platforms. Develop automation scripts to streamline DFT and test vector generation flows. Document verification methodologies, results, and best practices to enhance team efficiency. Innovate and implement advanced DFT solutions for next-generation nodes including 3nm and beyond. Skills Required: Strong hands-on experience in DFT design and verification methodologies. Expertise in scan insertion and ATPG for high-coverage test generation. Experience implementing MBIST architectures and memory test strategies. Knowledge of JTAG and boundary scan standards. Experience working with high-speed IPs such as HBM, DDR, and SerDes. Understanding of silicon bring-up, ATE validation, and yield analysis processes. Familiarity with deep submicron technologies and advanced node challenges. Proficiency in scripting for automation of DFT and test flows. Strong analytical and debugging skills in semiconductor environments. Education:

Bachelor's or Master's degree in Electrical Engineering or a related field.