Senior Design Verification Engineer

Principal Accountabilities

* Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect * Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics.

Job Complexity Minimum 6 years experience required in ASIC/FPGA verification ● Requires in-depth knowledge and experience ● Solves complex problems; takes a new perspective using existing solutions ● Works independently; receives minimal guidance ● Acts as a resource for colleagues with less experience ● Represents the level at which career may stabilize for many years or even until retirement ● Contributes to process improvements ● Typically resolves problems using existing solutions ● Provides informal guidance to junior staff ● Works with minimal guidance

Experience / Education Typically requires 6–7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.