Application Specific Integrated Circuit Design Engineer

All applicants must be EU citizens An innovative fabless semiconductor company that is expanding its Digital Design team in France with a Senior Digital ASIC Design Engineer. This position sits at the heart of the digital development team, with real ownership across architecture, RTL development and downstream implementation. As a Senior Digital ASIC Design Engineer, you will:

Define and implement complex RTL blocks from architectural specifications Lead digital work-packages from concept through to synthesized netlist Integrate multiple IPs at top level within a SoC environment Drive clock/reset domain strategy and manage multi-domain challenges Develop and maintain timing constraints for synthesis and implementation Perform design quality checks including Lint, CDC and RDC analysis

What They’re Looking For

All applicants must be EU citizens MSc or PhD in Electrical Engineering (or similar) Strong command of VHDL, Verilog or SystemVerilog Strong track record in digital IC or SoC development within advanced process nodes Exposure to high-speed interfaces such as PCIe, Ethernet or JESD-type protocols Confidence designing across multiple clock domains and low-power environments Background in mixed-signal environments is highly advantageous Strong communication skills in English

This role can also be based in Grenoble or Caen. Tel - 01189073075 LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/ #J-18808-Ljbffr