Senior Digital Verification Engineer — Lead with UVM & SV

A well-established European semiconductor company is seeking a Senior Digital Verification Engineer to join their growing team in Auvergne-Rhône-Alpes, France. This role involves defining verification strategies, building advanced UVM-based environments, and developing SystemVerilog testbenches. The ideal candidate will hold a Master's degree in Electronic Engineering and possess at least five years of industry experience, along with strong hands-on verification skills. This position offers a clear path to leadership and contribution to innovative projects. #J-18808-Ljbffr