Senior Digital ASIC Design Engineer – SoC RTL Lead (EU)

A semiconductor company is expanding its Digital Design team in Paris. They seek a Senior Digital ASIC Design Engineer to own architecture and RTL development in a collaborative environment. Responsibilities include leading digital work-packages, integrating IPs in a SoC, and ensuring design quality. Required qualifications are a master's or PhD in Electrical Engineering and a strong command of VHDL or Verilog. The role can also be based in Grenoble or Caen. #J-18808-Ljbffr