Staff / Sr Staff RTL Design Engineer

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Staff / Sr Staff RTL Design Engineer

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Alphawave Semi The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Alphawave Semi is expanding its team in connectivity networking products engineering Team. We are looking for experienced SoC RTL design engineers to contribute to our next generation connectivity networking products. This is an incredible opportunity to be part of the AI revolution and contribute to the complete semiconductor development cycle, from concept to product. The ideal candidate will have a strong and extensive background in RTL design across multiple projects. As an experienced RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. Why Join Us? Work on cutting-edge SoC designs in advanced process nodes. Products purpose-built for AI datacenter scale out and scale up connectivity Work in a high-impact, fast-paced environment. Competitive compensation and career growth opportunities. Work alongside some of the best minds in the semiconductor industry. What You'll Do Micro architect and RTL Design of SoC SubSystem/IP blocks Will develop UPF and run CLP checks Will be responsible for RTL quality checks - Lint/CDC/LEC Create appropriate documentation for hardware blocks Responsible for analyse / debug / fixing issues reported by verification team Will develop the synthesis constraints for the blocks / subsystem Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation What You'll Need Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies Experience in SerDes PHY, DSP, and Analog mixed signal is desirable Knowledge in Ethernet and PCIe standards is desirable Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Communication & Leadership: Team player with strong communication skills to ensure effective program execution. It Would Be Amazing If You Had Architecture: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Salary And Benefits Your contribution will be recognized with a base salary influenced by your qualifications, experience, location, and the internal equity of our team to ensure fairness and consistency across roles. In addition to our comprehensive benefits package, employees are also eligible for additional compensation opportunities. Health & Wellness programs that emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage. Comprehensive health plans Wellness Spending Account (WSA) Employee Assistance Program (EAP) Time Off Paid Vacation Paid Holidays Parental Leave Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

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