Lead Engineer - Physical Verification (Full Chip)

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

Lead Engineer - Physical Verification (Full Chip) SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast‑growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

Work on physical verification (DRC/LVS) of state‑of‑the‑art SOCs/ Digital IPs/ blocks at cutting edge FinFET technology nodes for various customers.

Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tapeout.

Work hands‑on to solve critical design and execution issues related to physical verification and sign‑off.

Own physical verification and sign‑off flows, methodologies and execution of SoC/cores.

Expertise in physical verification of SoC/ Full‑chip‑level and/or block‑level DRC, Experience and understanding of all phases of the IC design process from RTL‑GDS2 to LVS, ERC/ PERC, DFM, OPC , Tapeout process.

Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries.

Experience in debugging LVS issues at chip‑level with complex analog‑mixed signal IPs.

Experience with design using low‑power implementation (level‑shifters, isolation cells, power domain/islands, substrate isolation etc.).

Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full‑chip components.

Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch‑up etc.

Experience with ERC rules, PERC rules, ESD rules has an added advantage.

Requirements

BTech/ MTech/ PhD with 6-10 years of experience in physical verification.

Proven track record with multiple successful final production tape‑outs.

Proven ability to independently deliver results and be able to work hands‑on as and guide/help peers to deliver their tasks.

Be able to work under limited supervision and take complete accountability.

Excellent written and verbal communication skills.

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