Senior Chip Design Engineer

Overview

In this role, you will help create chip libraries, IP, and complete designs. You will utilize your expertise in SystemVerilog to contribute directly to our product development, working alongside a cross-functional team of world-class engineers and researchers. We’re looking for candidates who are passionate about pushing the boundaries of chip design, and excited to work at the intersection of semiconductors and AI. Key Responsibilities

Collaborate with ML and SW specialists as one of our domain experts Designing and operating novel chip design methodologies Qualifications

Bachelor’s or Master’s degrees in EE/CS 5-10 years of experience in RTL design Proficiency in the SystemVerilog language Experience with hands-on debugging – simulators, waveform viewing, coverage collection, etc Excellent written and verbal communication skills Comfortable working in a dynamic, research-heavy startup environment U.S. Citizen, Permanent Resident, or valid work visa Preferred Qualifications

Proficient in the use of Git (branches, pull requests, merging, rebasing, …) Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5, …) Experience writing timing constraints (SDC/TCL) Experience with FPGA development (Vivado, Vitis, Quartus, ACE …) What will help you thrive

Knowledge of open-source tools and contribution practices (Verilator, CocoTB, Yosys, …)

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