ASIC Verification Engineer — SystemVerilog/UVM Expert

A tech start-up in the semiconductor industry is seeking an experienced ASIC Verification Engineer to develop and implement verification plans for complex ASIC designs. The role involves designing testbenches, executing test cases, and collaborating with cross-functional teams to ensure the functionality and reliability of ASIC designs. Candidates should have a Bachelor's degree in Electrical or Computer Engineering, 3+ years of verification experience, and proficiency in Verilog and SystemVerilog. This position offers an annual salary range of $150,000 - $250,000 based on qualifications and experience. #J-18808-Ljbffr