Senior Digital Verification Engineer: RTL & UVM Lead

A leading technology firm is seeking a Lead Verification Engineer in Toronto to ensure high-quality digital RTL verification and develop reusable verification components. The successful candidate will contribute to various verification activities and must possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science. Familiarity with SystemVerilog, UVM, and scripting languages is preferred. The role involves collaboration across teams and requires full-time presence in the Toronto office, with minimal travel expectations. #J-18808-Ljbffr