Principal STA Engineer | Irvine, CA

Celero Communication Inc. is an exciting and fast-growing start‑up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

We are seeking a highly experienced

Principal STA Engineer

to play a key technical leadership role in the development of next‑generation semiconductor products. In this role, you will own complex blocks and full‑chip STA analysis, and act as a technical authority within the Physical Design team.

You will work closely with architecture, RTL, DFT, and sign‑off teams to deliver high‑performance, low‑power, and area‑efficient designs in advanced technology nodes.

This role is ideal for a senior individual contributor who thrives on solving the hardest physical design problems and mentoring other engineers.

Key Responsibilities

Own end‑to‑end timing analysis for large blocks and full chip:

Implement Foundry sign‑off into Tempus/PrimeTime sign‑off requirements

Validate SDC constraints

Drive sign‑off closure across:

Produce timing ECOs for blocks and top level

Run back‑annotated IR timing analysis

Run Noise and crosstalk analysis

Technical Leadership

Act as a technical lead on STA

Define and review physical design methodologies and best practices.

Mentor and guide junior and senior PD engineers.

Lead design reviews and tape‑out readiness.

Cross‑Functional Collaboration

Partner with RTL, Architecture, DFT, Analog, and Verification teams.

Provide early STA feedback on:

Power and area trade‑offs

Advanced Node Expertise

Drive implementation on advanced nodes (e.g., 7 nm, 5 nm, 3 nm).

High‑frequency datapaths

Large memory subsystems

Multi‑clock and asynchronous domains

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering or related field.

5+ years of experience in STA.

Proven ownership of multiple successful tape‑outs.

Strong hands‑on experience with STA tools (PrimeTime/Tempus).

Deep understanding of:

Timing closure

Power integrity

Clocking methodologies

DFT timing requirements

Preferred Qualifications

Experience with AI accelerators, CPUs, GPUs, or high‑speed SoCs.

Expertise in advanced nodes (5 nm and below).

Knowledge of:

High‑speed interfaces (DDR, HBM, PCIe)

Multi‑voltage and multi‑clock domains

Chiplet‑based architectures

Salary Range $150,000 - $250,000 Base Annually The final offer will be determined based on job‑related skills, experience, qualifications, and location.

As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.

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