Lead ASIC Verification Engineer - SystemVerilog/UVM Expert

A global technology leader is seeking a Principal ASIC Verification Engineer in Ottawa, Canada. This role involves developing and verifying advanced SoCs, leading testing strategies, and collaborating with diverse teams. Candidates should have over 8 years of ASIC verification experience, proficiency in SystemVerilog and Python, along with strong problem-solving skills. The company values innovation and offers a diverse, inclusive work culture, continuous learning opportunities, and well-being programs. #J-18808-Ljbffr