Lead SoC Verification Engineer - Sign-Off & Tapeout

A semiconductor consultancy is seeking a Lead Engineer for Physical Verification in Toronto. The role involves working on the verification of state-of-the-art SOCs and Digital IPs, focusing on DRC/LVS at advanced technology nodes. Candidates should have 6-10 years of experience in physical verification, a proven track record of successful tape-outs, and excellent communication skills. This position offers the opportunity to tackle critical design issues and lead verification methodologies in a collaborative environment. #J-18808-Ljbffr