Senior ASIC Design Engineer – RTL, Synthesis & AI/HPC SoCs

A leading semiconductor design firm in Toronto, Canada is seeking a Senior ASIC Design Engineer to tackle challenges in AI and HPC SOCs. The role involves translating system-level requirements into detailed design specifications and developing synthesis constraints for complex designs. Ideal candidates will have 8+ years of experience in ASIC design, proficiency in RTL logic (Verilog/System Verilog), and a strong foundation in lab troubleshooting. This position offers an attractive compensation package, including a salary from $140,000 to $190,000. #J-18808-Ljbffr