Lead ASIC Front-End Synthesis and Timing Engineer

A global technology leader in Ottawa is looking for an experienced individual for front end ASIC implementation. This role involves executing synthesis, timing analysis, and validation processes while collaborating with various teams to ensure high performance in optical networking technologies. Applicants should possess a B.Sc. in Electrical Engineering or a related field, along with experience in ASIC development environments and strong familiarity with RTL design principles. A competitive salary and benefits package are offered. #J-18808-Ljbffr