Manager - Design Verification

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

Collaborate with architects, hardware engineers,and firmware engineers to understand the new features to be verified. Build test plan documentation, accounting forinteractions with other features, the hardware, the firmware, and thesoftware driver use cases. Estimate the time required to write the newfeature tests and any required changes to the test environment. Build the directed and random verification tests. Debug test failures to determine the root cause;work with RTL and firmware engineers to resolve design defects and correctany test issues. Review functional and codecoverage metrics - modify or add tests or constrain random tests to meet thecoverage requirements.

Requirements

Proficient in IP level ASIC verification.

Proficient in debugging firmware and RTL codeusing simulation tools.

Proficient in using UVM test benches and workingin Linux and Windows environments.

Experienced with Verilog, System Verilog, C, andC++.

Graphics pipeline knowledge.

Developing UVM based verification frameworks and test benches, processes and flows.

Automating workflows in a distributed computeenvironment.

Exposure to simulation profile, efficiencyimprovement, acceleration, HLS tools/process.

Strong background in the C++ language, preferablyon Linux with exposure to Windows platform.

Good understanding and hands-on experience in theUVM concepts and SystemVerilog language.

Good working knowledge of SystemC and TLM withsome related experience.

Scripting language experience: Perl, Ruby, Tcl, shell preferred.

Exposure to leadership or mentorship is an asset.

Desirable assets with priorexposure to video codec system or other multimedia solutions.

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