Lead Front-End Engineer — Digital IP & Signoff

A semiconductor consulting company is seeking a Front-End Lead Engineer in Toronto. This role involves leading the design and signoff of high-performance digital IP blocks while mentoring junior engineers. The ideal candidate will have 6–8 years of experience in ASIC front-end design, proficiency in Verilog/System Verilog, and strong problem-solving skills. Join a fast-growing team committed to delivering exceptional semiconductor design services. #J-18808-Ljbffr