Senior ASIC Design Engineer – RTL, Synthesis & AI/HPC SoCs

A technology design company in Toronto seeks a Senior ASIC Design Engineer with over 8 years of ASIC experience. The role involves translating requirements into architecture specifications and designing complex RTL logic. Candidates should be proficient in Verilog and System Verilog and have experience in troubleshooting at the system level. A compensation range of $140,000 to $190,000 plus bonuses is offered, reflecting the candidate's skills and experience. #J-18808-Ljbffr