ASIC DV Engineer – UVM, Formal & Power

A leading semiconductor company is seeking an experienced ASIC Design Verification Engineer to join their team in Vancouver. The role involves developing testbenches, managing verification methodologies, and enhancing RTL design quality. Candidates should have a degree in electrical or computer engineering and significant hardware verification experience. Collaboration and effective problem-solving are essential in this dynamic environment. The company values innovation and continuous learning. #J-18808-Ljbffr