Senior ASIC Verification Engineer: UVM & PCIe Expert

A leading electronic design firm based in Toronto is seeking a Senior ASIC Verification Engineer to join their talented team. This role involves verifying blocks and subsystems in high-speed interfaces and networking protocols using SystemVerilog and UVM. Candidates should have over 8 years of experience in ASIC verification, possess deep expertise in Verilog and SystemVerilog, and demonstrate strong communication skills. Competitive compensation package ranging from $120,000 to $170,000 plus benefits is offered. #J-18808-Ljbffr