Lead Engineer - Digital Design

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description JobTitle:

Front-End Lead Engineer

JobType:

Full-Time

Experience Level:

Lead Engineer

Years ofExperience:

6–8 Years

Role Overview The Front-End Lead Engineer will drive the design, development, and signoff of high-performance digital IP blocks and subsystems while leading Functional ECO implementation at the netlist level. This role requires strong technical leadership across the front-end design flow, including RTL development, verification coordination, synthesis, signoff, and Functional ECO execution. You will collaborate with cross-functional teams, ensure design quality, and mentor junior engineers to build technical depth within the organization.

Key Responsibilities Front-End Design & Signoff

Drive design signoff activities: lint, CDC/RDC, synthesis

Lead the front-end development of digital IP blocks or subsystems from concept to implementation

Collaborate with architects, verification, physical design, firmware/software teams, and program managers

Support P&R and signoff teams with RTL fixes, constraints, and ECO requirements

Own schedules, deliverables, and quality for the front-end engineering team

Mentor junior engineers in RTL design, ECO implementation, verification practices, and signoff flows

Drive continuous improvement of front-end methodologies, automation, and best practices

Required Skills

Strong hands‑on experience across ASIC front-end design flow

Exposure to Functional ECO flows using Synopsys Formality ECO and/or Cadence Conformal ECO

Proficiency in Verilog/System Verilog, gate-level netlist editing, and scripting (TCL, Perl, Python)

Solid understanding of timing analysis, STA constraints, and physical design interactions

Strong background in formal verification, simulation, debugging, and issue closure

Excellent analytical and problem‑solving skills with attention to quality and detail

AMD experience is an added advantage

Preferred Qualifications

Bachelor’s or Master’s degree in Electrical/Electronics Engineering

Strong foundation in digital design principles and problem‑solving skills

AMD experience is an added advantage

Requirements

Years of Experience: 6–8 Years

Bachelor’s or Master’s degree in Electrical/Electronics Engineering

Strong foundation in digital design principles and problem‑solving skills

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